求才人數：3

計薪方式：依學經歷、證照核薪(每月經常薪資達4萬元以上) 

1. Responsible for test chip physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.

2. Responsible for physical verification including DRC, LVS and ESD checking.

3. Working on advanced process node design methodology, PD execution and sign-off

工作年資(經歷)：4年以上

求才人數：2

計薪方式：依學經歷、證照核薪(每月經常薪資達4萬元以上) 

1. To develop and maintain Front/Back-end design flow 、Verification flow 、Sign-off flow、Power/IR flow 、Timing/LVF characterization flow
2. To develop and maintain Standard cell library flow、Analog & Mixed Signal design flow
3. To develop in-house EDA/CAD utility

工作年資(經歷)：4年以上