求才人數:3
計薪方式:依學經歷、證照核薪(每月經常薪資達4萬元以上)
1. Responsible for test chip physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
2. Responsible for physical verification including DRC, LVS and ESD checking.
3. Working on advanced process node design methodology, PD execution and sign-off
工作年資(經歷):4年以上
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